KiCad First PCB Design: From Schematic to Gerbers

The hard part of a first PCB is rarely drawing a trace. It is keeping the electrical design, physical parts, fabricator limits, and exported files in agreement. The reliable order is schematic, ERC, footprints, board setup, placement, routing, DRC, then manufacturing output.

Build the schematic before opening the board editor

Start a new KiCad project with File > New Project. KiCad creates the project file, schematic file, PCB file, and supporting folders together. Keep those files in one project directory; moving only the schematic later can break the project’s expected paths.

Open the schematic in Schematic Editor and place symbols with Place > Add Symbols. A symbol describes electrical connections: pin names, pin numbers, power pins, and the nets joining them. It does not describe the physical copper pattern.

A footprint does something different. It defines the physical pads, pad numbers, courtyard, silkscreen, mounting holes, and component body area. The symbol and footprint are assigned separately, and matching their pin numbers is the part that prevents many first-board failures.

For a small controller board, place connectors, power entry, protection parts, regulators, the controller, and external loads in a readable signal flow. Use net labels instead of dragging long wires across the page. Add power symbols where they clarify intent, then run Tools > Annotate Schematic before assigning footprints. Reference designators such as R1 and U1 must be stable before the board is populated.

Use Place > Add Text for notes that matter during assembly, such as connector orientation or an unpopulated option. Notes are not a substitute for a connection. A label must be attached to the intended wire or pin, and a power symbol must be electrically connected rather than merely placed nearby.

For every unused pin, follow the component datasheet and KiCad’s electrical rules. Some pins may need a no-connect flag, placed with Q. Others must be tied to a defined level or left open under a documented condition. Do not mark a pin no-connect just to silence a warning.

The first setup decision that changes the rest of the project

Set the schematic page and grid to values that make the drawing readable, but do not confuse schematic grid settings with PCB manufacturing precision. The board’s real limits are set later in PCB Editor > File > Board Setup.

Every fabricator has different minimum track widths, clearances, via sizes, drill limits, and copper-layer options. Obtain the intended fabricator’s capability table, then enter values under Board Setup > Design Rules > Net Classes and add custom rules under Custom Rules only where the design needs them.

Run ERC before assigning physical parts

Electrical Rules Checker is available from Inspect > Electrical Rules Checker in Schematic Editor. Run it before moving into PCB layout. ERC checks the logic represented by the schematic: unconnected pins, conflicting drivers, missing power drivers, suspicious pin types, and other connection problems.

Read each marker rather than deleting all violations. A warning about a connector pin may be expected, but the exception should have a reason. Use the violation context menu to exclude a known case only after checking the datasheet and the intended circuit. An ignored error can hide a later revision mistake.

ERC and DRC answer different questions:

Open the ERC violations panel and fix real errors at the source. If a net is meant to be connected, repair the wire or label. If a pin is intentionally unused, place the correct no-connect flag. Re-run ERC until the remaining exclusions are understood.

Assign footprints and transfer the netlist

Assign physical packages with Tools > Assign Footprints. This is where the symbol-to-footprint decision becomes concrete. A resistor symbol may receive a 0603, 0805, or through-hole footprint. Those options have different pad sizes, assembly constraints, hand-soldering access, and voltage or power implications.

Filter the footprint chooser by library and pin count, then inspect the preview. Check these items against the component drawing and datasheet:

• Pad numbers match symbol pin numbers.
• Pin 1 marking agrees with the component body and datasheet.
• The package pitch and body dimensions fit the actual part.
• The courtyard leaves enough space for assembly and rework.
• Connector orientation matches the direction cables will approach.
• Thermal pads, exposed pads, mounting holes, and keepouts are represented correctly.

For a first board assembled by hand, our choice is usually a package that leaves a sensible soldering margin rather than the smallest available package. The smaller footprint saves board area, but it does not solve an electrical problem and can make inspection harder. Do not buy a microscope or move to fine-pitch packages until the board actually requires that density.

Save the assignments, then use Tools > Update PCB from Schematic in PCB Editor. In older KiCad releases this command may appear under the Tools menu with slightly different wording. The transfer brings in footprints and ratsnest connections; it does not decide where parts belong.

Draw the board outline and place parts by function

In PCB Editor, set the working layer to Edge.Cuts and draw a closed outline using Place > Add Graphic Rectangle, Place > Add Graphic Line, or arcs where the shape requires them. The outline must be a single, closed boundary with no accidental gaps or duplicate edges. Keep mounting holes and board cutouts represented according to the fabricator’s file requirements.

Set the board origin deliberately. A corner or mounting reference point is easier to measure than an arbitrary cursor position. Use Grid settings and the Properties panel to enter dimensions instead of relying on visual alignment.

Place footprints with M and rotate with R. Start with fixed geometry: mounting holes, board-edge connectors, switches, displays, and parts with height restrictions. Then place the power path, controller, clocks, analog sections, and external interfaces. Keep noisy switching nodes and high-current loops physically short. Put decoupling capacitors close to the relevant power and ground pins, with a short path to each.

Do not route while the placement is still uncertain. Placement determines trace length, return paths, thermal spacing, and whether a board can be assembled. Ratsnest lines are useful here: a cluster of crossing connections usually signals a placement problem, not a routing challenge.

Before routing, inspect Board Setup > Design Rules > Net Classes again. Assign power, signal, clock, and sensitive analog nets to appropriate classes. The correct width depends on current, copper thickness, allowable temperature rise, layer count, and the fabricator’s process. Use a trace-width calculator or the fabricator’s guidance for power conductors rather than copying a tutorial value.

Route, inspect, and run the final DRC

Route interactive tracks with X. Choose the copper layer with V to place a via while routing, if the stack-up and fabricator allow it. Use the shortest sensible path for sensitive or fast signals, but do not make every trace artificially short at the expense of a clean return path.

A ground plane is normally added with Place > Add Filled Zone. Select the copper layer, assign the ground net, set the clearance and minimum width from the board rules, then draw the zone around the board. Press B to refill zones after changes. Inspect thermal relief connections and make sure a dense area has not been isolated from the plane.

Before final DRC, verify that intended connections have no unrouted ratsnest lines; silkscreen text does not cover pads or the board edge; pin 1, polarity, connector orientation, and mounting-hole positions are clear; copper is not too close to edges, holes, slots, or exposed mounting hardware; courtyards do not overlap in a way that prevents assembly; and height restrictions are respected.

Run Inspect > Design Rules Checker. DRC checks the physical board against the rules configured in Board Setup and verifies manufacturability against the fabricator’s limits. It must be run before exporting manufacturing files. A board that looks correct in 2D can still fail on clearance, hole size, board-edge spacing, courtyard overlap, unconnected copper, or a missing connection.

Do not dismiss every DRC marker because the board is only a prototype. Review the item, inspect the surrounding geometry, and change the layout or rule when the violation is real. Use an exclusion only for a deliberate exception that has been checked against the fabrication process.

Generate Gerbers, drills, and a repeatable release

When the schematic and PCB are stable, save all files and run DRC again. In PCB Editor, open File > Fabrication Outputs > Gerbers. Select the copper layers, solder mask, silkscreen, paste layers if assembly needs them, and Edge.Cuts. Use the plot settings required by the fabricator, then plot the files.

Open File > Fabrication Outputs > Drill Files and generate the Excellon drill file. Include plated and non-plated holes according to the board’s actual construction and use the same origin and units as the Gerbers. If slots are present, verify how the chosen fabrication process expects them to be represented.

Inspect the generated files in a Gerber viewer, not only in KiCad. Check the board outline, layer alignment, pad shapes, hole positions, polarity marks, and text. A missing Edge.Cuts layer or an outline plotted on the wrong layer can produce a file set that looks complete in a directory while describing the wrong board.

Keep the manufacturing output in a release folder with the KiCad project, a readme containing the stack-up and special notes, and the DRC result. If a revision changes the board, change the revision text and regenerate every output. Never mix Gerbers from one revision with drill files from another.

Frequently asked questions

Should I route before running ERC?

No. Run ERC after the schematic is connected and annotated, then correct the electrical design before footprints and routing. Routing a board built from an incorrect netlist creates work that must be discarded.

Do symbols and footprints have to come from the same KiCad library?

No. A symbol defines the circuit connection and a footprint defines the physical pads and body geometry. They can come from different libraries, provided the footprint’s pad numbers match the symbol’s pin numbers and the physical part matches the footprint drawing.

Why does my DRC pass while the fabricator still rejects the board?

KiCad only checks the rules configured in your project. If the net classes, hole limits, copper layers, board-edge clearance, or manufacturing constraints do not match the fabricator’s limits, DRC can pass an unsuitable board. Update Board Setup with the actual process rules, rerun DRC, and inspect the exported Gerbers and drill files.

We build this kind of work to order through custom electronics and smart systems.